🔧 Google Silicon Architecture/Design Engineer, PhD – Early Career (Bengaluru)
Are you a PhD graduate in electronics or computer engineering with an interest in next-gen AI hardware? Google is hiring a Silicon Architecture/Design Engineer (PhD, Early Career) in Bengaluru, India, to innovate and scale the core hardware powering AI/ML workloads like TPU. Join a visionary team shaping the future of hardware acceleration.
🧠 About the Role
As a Silicon Architecture/Design Engineer, you will define and build architecture specs, performance models, and design next-generation TPU accelerators. Your work directly influences Google’s AI infrastructure used by products worldwide.
Work Location: Bengaluru, Karnataka, India (On-site)
Organization: Google’s ML, Systems & Cloud AI (MSCA) hardware group
🎓 Eligibility Criteria
Minimum Qualifications:
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PhD in Electronics & Communication, Electrical Engineering, Computer Engineering, or related technical fields, or equivalent experience
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Experience with accelerator architectures and data center workloads
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Proficient in C++, Python, Verilog, and using Synopsys or Cadence EDA tools
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~2 years post-PhD experience
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Expertise in performance modeling tools and memory hierarchies, bus architecture, arithmetic units
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Proficiency in high-performance and low-power design techniques
💼 Responsibilities & Day-to-Day
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Architect and model AI/ML accelerators (TPUs) for future workloads
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Collaborate closely with hardware/software architects, ML researchers, and compiler teams
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Define and validate design specifications based on system-level performance and efficiency
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Apply modern hardware design techniques for high efficiency at scale
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Test and validate low-power architectural choices and data center optimizations
📊 Quick Summary Table
| Category | Details |
|---|---|
| Job Title | Silicon Architecture/Design Engineer, PhD, Early Career |
| Company | Google – ML / Systems & Cloud AI Hardware Group |
| Location | Bengaluru, Karnataka, India |
| Employment Type | Full-time – Early Career (Mid-level) |
| Education | PhD in relevant fields |
| Experience Required | Accelerator architecture, data center workloads, toolchain usage |
| Preferred Experience | 2 years post-PhD, performance modeling, low-power design skills |
| Languages & Tools | C++, Python, Verilog, Synopsys/Cadence EDA tools |
| Key Focus Areas | TPU architecture, high-performance memory/bus design |
| Work Model | On-site in Bengaluru |
✨ Why This Role Stands Out
1. Direct AI Hardware Impact
Help design future TPU generations that power Google’s global AI services and Cloud infrastructure.
2. Work with Cross-disciplinary Technical Teams
Collaborate with hardware architects, ML researchers, compilers teams, and system designers to bring ideas into silicon.
3. Learn at Scale
Google’s hardware design teams use industry-leading tools and workflows across architecture, modeling, and validation.
4. Ideal for Early-Career PhD Graduates
Gain domain specialization in silicon architecture, performance modeling, and accelerator systems early in your career.
💡 Application & Preparation Tips
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Share your publications or projects related to hardware architecture, digital design, or accelerator systems
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Highlight your familiarity with CAD tools and performance modeling tools
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Demonstrate expertise in C++, Python, Verilog, and system-level design choices
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Discuss hardware-software interaction, power-efficiency strategies, or data center customization in your interviews
🛠 Why You Should Apply Today
If you’re a PhD graduate excited about designing hardware for AI workloads and want to work at Google’s hardware center in Bangalore, this role is a rare opportunity to scale your expertise. Apply now to help design the next wave of AI-powered chips that serve billions of users.
Click Here to Apply Now Google Silicon Architecture Engineer PhD 2025
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